At Embedded World, Mark Throndson spoke on “Networking Native RISC-V Processor for the Datacenter,” discussing several optimizations that can be achieved within a standard #RISCV solution that tailor the implementation to networking. He highlighted the multi-threaded, award-winning MIPS I8500, which implements a big-endian-native #CPU and compute cluster, allowing for packet header and payload data to be natively processed in network byte order, removing the overhead of performing any byte swizzling within hardware gates or in software instructions.