So, I've been secretly making a Factorio-like game for about a year now. I was planning to release it maybe a few months ago, ahead of the big Factorio update. But now that's in a few weeks, and my game's not quite ready. What should I do? Any gamedev folks have advice?

You should consider hiring my extremely smart close friend Chris McNally, who just completed his PhD at MIT doing quantum type theory/compilers. His advisor and his labmates were freely describing him as literally the smartest person in the group, and he's looking for jobs right now! He might sign one offer, but he's looking at other options before he signs. If you can interview him and do your whole process in <2 weeks, I highly recommend folks talk to him right now, it's a great opportunity to snap him up for some mathy softwarey role. Feel free to DM me, and I can pass on his resume, and put you in touch with him.

Basically, he got to the acknowledgement slide for his parents and sister, and he couldn't quite get the words out to thank them, with a few restarts, and it made me (and several others) cry.

I'm 3 out of 3 for crying at weddings I've been to, but now I'm 1 out of 2 for crying at thesis defenses! For the weddings, what made me cry in all three cases was the bride getting choked up and being unable to get her words out, and at the thesis defense it was the same!

Okay, deleting this post because apparently commenting at all on this topic brings out hordes of physics crackpots. (Also maybe I want to be calling work "frankly embarrassing" less, as maybe that's kind of dunking.)

My final objection: Even if the paper does, somewhere among all the bizarre arguments, correctly cite an argument that our universe supports hypercomputation, you still can at most say "a purported universe simulator *also* requires hypercomputation", you can't rule it out!

Further, the paper cites the Penrose-Lucas argument (that humans are somehow magically immune to Gödel's incompleteness theorem) as though it were an accepted fact, rather than being widely rejected as basically nonsense. This feels somewhat disqualifying to me.

It is possible that I do not understand enough of these citations, and I am misunderstanding the argument, but I can at the very least say that even if these are good arguments for "the universe is doing something uncomputable", they have certainly mixed them with bad arguments.

Like, I'm clearly not cheating at all, this exemption is obviously designed for things like my business, if I'm understanding this text correctly.

Does anyone else know about this? Has anyone here successfully ordered PCBs from JLCPCB or PCBWay (or another Chinese shop) and gotten it tariff free as a prototype? All of my boards are prototypes right now; I'm clearly exactly what the linked law is talking about.

For transparency, I'm deleting this post. I think it might have been mild misinformation. After a lot of struggling, it looks like maybe the latest wasm-bindgen fixes the edition 2024 issue? I'm not done updating everything yet, though, it's a lot of work.

I understand that an unstable feature might be removed, but I *really* think "we removed this unstable feature, but decided to *add* it to the next edition" is crazy.

(I know this is super duper basic to many of you, but I actually hadlready done a *lot* of electronics before anyone told me that sharp rise times can be inherently problematic, so I'm posting this in case someone hasn't learned this yet!)

When I was younger I figured the ideal eye diagram looked like a square wave. Why not have the sharpest possible edges? Assuredly that's just more SI budget, I thought, staying even further from the forbidden area. But no, an ideal eye *is* rounded! Your rise time should be just fast enough to make a nice open eye, and no more, to minimize harmonic content. This is why slew rate control is so important; a faster rise time just puts extra energy into the transmission line, and if there are any frequency-dependent effects (which there will be!) they can easily result in all sorts of overshoot/ringing issues. Now that cheapo microcontrollers (like the RP2040) can do 100+ MHz IO, and often have nanosecond-scale rise times, I'm starting to wish that programmable slew rate control were a more standard feature! (Image credit: incompliancemag.com/use-the-…)

I’m in Manhattan for the day, free after about 4PM. If anyone wants to meet up, feel free to DM me!

(Image credit is unclear. I found it here, where it is posted without credit: cs.stackexchange.com/questio… It says "royal institute of technology" in the top left, but I didn't try to track down the original source.)

Here's something I've wanted to see for a while, that I've literally never seen: A pipeline diagram that *includes* retiming. For example, the green boxes are the logical registers, but what if after retiming it becomes the cuts I've drawn in pink? I've never seen such a diagram!

I knew I'd get spam if I put up a "contact me" form on our company website. What I wasn't prepared for was the sheer quantity of pavement sealing companies who want to seal our precious precious pavement.

I know many people have made this observation, but it's so funny that the assumptions about high-end computing needs has gone from overwhelmingly FP64 ("FP32 is just for gamers, serious HPC is FP64"), to now being FP16 or even 8-bit to 4-bit for ML. It's a complete reversal.

(This was at @redwood_ai. It was a great time to work there, with a ton of fun work happening.)

Many years ago I wrote an LD_PRELOAD that would sneakily turn every cudaMalloc in pytorch into a cudaMallocManaged. It actually just kind of worked, for running huge >VRAM models. I keep expecting this to be a standard feature, or someone else to have done this. Is this a thing?