This patch is just a sync with the 59th ISE [5].
There has been example in the past, that ISE was misleading: the final #GraniteRapidsD supports the entire #AVX10_1 with dual 512b-FMAs [6]
3/4
#Intel refreshed the #AVX10_1 specification to 3.1:
cdrdv2-public.intel.com/8484…
x.com/InstLatX64/status/1818…
7/8
#Intel refreshed the #AVX10_1 specification to 3.0:
cdrdv2-public.intel.com/8289…
128-bit vector support removed
I disagree:
- preAVX512 is much more difficult, but interestingly there is much less complain about it;
- in #GraniteRapids, #AVX10_1 is introduced with a serious ISA defragmentation, and the old numbering schema is back (e.g. SSE4.2);
#AVX512_FP16 on #Zen6 is my expectation based on the second slide:
#Intel refreshed the #AVX10_1 specification to 3.0:
cdrdv2-public.intel.com/8289…
128-bit vector support removed
#Intel refreshed the "Intel Advanced Vector Extensions 10 Architecture Specification" to 2.0:
This is still just AVX10.1 with modifications, not AVX10.2!
cdrdv2-public.intel.com/7955…
#AVX10 #GraniteRapidsD #GraniteRapidsX
