If you're writing assembler, I heartily recommend Compiler Explorer. I wrote about this from a RISC-V perspective a while back. #asm #riscv projectf.io/posts/riscv-comp…

Excited to bring @DeepComputingio + @risc_v + @FrameworkPuter to @FOSS_for_All — sharing the power of open computing with the community! #RISCV #Opensource

New episode of the AI Master Podcast is out! 🎧 Guest: Christian Stenzel, Director of Sales EMEA at @tenstorrent We talk about open AI hardware, RISC-V, chiplets, and the future of silicon. Listen on your favorite platform! #AIMasterPodcast #AI #RISCv #Tenstorrent #OpenHardware

C107は落ちましたので例によって@tceoo1さんの所に 委託の予定です。 新作は以下の2点+αのとなる予定です。 ・DTMFデコーダIC 改 ・低ピン数スイッチマトリクス読取回路基板(仮) 　with RISC-V命令デコード表示ファームウェア (・拙作の技術解説ペーパーorコピー本) #C107 #riscv

📢 RISC-V Open Hours 🗓️ Thu, Nov 13, 11:00 AM – 12:00 PM (GMT+8) 🔗 Event: community.riscv.org/events/d… ✨ Community forum beyond mailing lists ✨ Focus on RISC-V in open source projects & dev boards ✨ Updates, tech topics & new ecosystem highlights 🚀 #RISCV #RVOH @risc_v

At Embedded World, Mark Throndson spoke on “Networking Native RISC-V Processor for the Datacenter,” discussing several optimizations that can be achieved within a standard #RISCV solution that tailor the implementation to networking. He highlighted the multi-threaded, award-winning MIPS I8500, which implements a big-endian-native #CPU and compute cluster, allowing for packet header and payload data to be natively processed in network byte order, removing the overhead of performing any byte swizzling within hardware gates or in software instructions.

💡 Every AtlasChip carries a blockchain identity — making technology transparent, traceable, and trustworthy. Investment link 👇 sidrastart.com/project/3f4e7… #AtlasChipWeb3 #RISCv #SmartTech #HalalFinance

Compiler Explorer is a great way to understand the effect of #riscv extensions or compare CPU arch. You can even compare rv32 and armv7 to a 486. 🤔 For example, an endian swap takes 11 instructions with the base RISC-V ISA, but only 1 instruction (rev8) with the Zbb extension.

How to setup an OpenBSD RISCV64 Virtual Machine in QEMU - Post by Hiltjo Posthuma #OpenBSD #RiscV codemadness.org/openbsd-risc…

Why is Rialo a game-changer? We're leveraging RISC-V smart contracts to deliver unmatched speed, security, and scalability. It’s the Web3 infrastructure you wished for—built to handle billions of users. Ready to ditch the lag? @RialoHQ #RISCV #Scalability #FutureOfWeb3 @RiscVFdn

Green screen #DOOM ! This was my favourite bug we found running DOOM on the @Tenstorrent Ascalon #RISCV CPU in pre silicon testing. We initially thought it was a chip RTL issue, but it turned out to be both a gcc bug gcc.gnu.org/bugzilla/show_bu… and a QEMU bug lists.nongnu.org/archive/htm…

Thanks @risc_v for the invite to give a keynote at #RISCVSummit a couple of weeks ago. We have seen great progress in #RISCV for #HPC, and given promises by vendors and progress in the sw ecosystem I predict that 2026 could be a watershed year. piped.video/ItA-NS4vxsU?si=p2ZW…